1. Field of the Invention
The present invention generally relates to a semiconductor structure and fabrication therefor. More particularly, the present invention relates to a semiconductor structure having a dielectric material.
2. Description of Related Art
Recently, in the development of semiconductor process, the size of the component is minimized to sub-micron level. Therefore, in order to reduce the retardation time (RC time delay) of the transmission of the metal line, conducting wire made of the copper (Cu) is used instead of the aluminum (Al) because the resistance of copper is lower than that of the aluminum. In addition, the use of low dielectric constant (low-k) material for achieving high operating speed is also known. In general, the conventional low dielectric constant (low-k) material may be classified into spin on coating low-k material and chemical vapor deposition (CVD) low-k material by the deposition method. However, the conventional low dielectric constant (low-k) material may be classified into inorganic low-k material, organic low-k material and inorganic/organic combined low-k material by the component of the material.
Hereinafter, the conventional dual damascene structure will be illustrated and described. FIG. 1 is a cross-sectional view schematically illustrating a conventional dual damascene structure. Referring to FIG. 1, the conventional dual damascene structure 100 includes a substrate 102, a first dielectric layer 104, a first hardmask layer 108, a via 106, a second dielectric layer 110, a second hardmask layer 114 and a trench 112. In general, since the dielectric constant of the organic dielectric material is lower than that of the inorganic dielectric material, the organic dielectric layer is advantageously applied. In addition, the process of using the organic dielectric material is different from the process of using the inorganic dielectric material. For example, generally the characteristic and property of etching of the low-k organic dielectric material are similar to that of the photoresist layer, i.e., the etch selectivity is poor. Therefore, in the manufacturing process, before the photoresist layer is formed, a hardmask layer such as a metal layer an inter-metal compound layer is formed to serve as an etching mask for the subsequent steps. However since the surface property of the organic dielectric material and that of the hardmask layer are different, defects are easily generated during the formation of the hardmask layer.
In addition, the surface of the low-k organic dielectric layer is generally hydrophobic. Therefore, when a wet process is performed to the surface of the low-k organic dielectric layer, water marks are easily formed on the surface thereof. In other words, the surface of the low-k organic dielectric layer is not suitable for wet process.
Moreover, during the etching of the low-k organic dielectric layer, polymer residues are easily generated that would deposit on the edge of the wafer. The residues will adversely influence the subsequent process.
Accordingly, a semiconductor process capable of reducing the defects and reducing formation of water marks on the low-k dielectric material is highly desirable. Further, a process of easily removing the polymer residues from the edge of the wafer is also highly desirable.